FIG. 1 shows a data transmission system according to the prior art. A transceiver, or a transmitting and receiving circuit, receives transmitted data from a data source and sends these as an analog transmitted signal to another transceiver via a data transmission line. The data transmission line is, for example, a two-wire telephone line made from copper. In this case, the transceiver at the exchange end COT (central office terminal) constitutes the clock master, that is to say the transmitted signal is emitted at the exchange end synchronously with a clock signal of the transceiver. The transceiver at the subscriber end RT forms the so-called clock slave, that is to say the clock signal recovered at the receiving end is used as the transmitting clock thereof.
In the event of defective synchronization of the transceiver RT at the subscriber end, the clock frequency of the transmitted signal corresponds exactly to the clock frequency of the received signal. Consequently, the clock regulation circuit of the transceiver at the exchange end need only set the exact sampling phase in the receiver included therein. The sampling phase is a function in this case chiefly of the signal propagation time of the transmission line.
In the data transmission system illustrated in FIG. 1, the data are transmitted simultaneously in both directions via the transmission line. This is therefore a so-called full duplex data transmission system. The analog received signal of a transceiver is composed in this case of two signal components, specifically the transmitted signal emitted by the opposite transceiver, and the signal component coupled in by its own transmitting device, or the echo signal component. The echo signal component in this case constitutes interference, and is compensated in the receiver of the transceiver by means of an echo compensation circuit. The echo compensation circuit within the transceiver in this case calculates as accurately as possible an estimate for the echo signal component and subtracts the latter from the received signal.
In digital data transmission, the transmitter sends at a symbol rate 1/T which is not known at the receiving end. As a rule, the frequency and phase of the transmitting and receive clock deviate from one another. When the transmitting and receive clocks deviate from one another, the sampled received signal differs from the transmitted signal. In order to recover the original transmitted signal, it is necessary for the receiver clock signal to run at the same frequency as the clock signal of the transmitter. It is necessary, moreover, for the receiver clock signal to have the same phase as the transmitted signal.
FIG. 2 shows a conventional transceiver according to the prior art. The transceiver consists of a transmitted signal path and a received signal path. The transmitted data and/or transmitted data symbols are firstly fed in the transmitted signal path to a transmitting filter, and subsequently converted into an analog transmitted signal by means of a digital-to-analog converter. The analog transmitted signal is supplied to a hybrid circuit in a fashion amplified with the aid of a driver circuit. The hybrid circuit is connected to the data transmission line.
At the received signal path, the received analog signal is firstly filtered by an analog received filter EF, and subsequently sampled. The sampling is performed within a sampling circuit which either consists of an analog-to-digital converter or, as illustrated in FIG. 2, an analog-to-digital converter, an interpolation filter IF and a downstream interpolator. The analog-to-digital converter in this case samples the analog received signal with the aid of a freerunning operating rate signal. The sampled signal is subsequently fed to the digital interpolation filter IF and interpolated by the interpolator. The interpolator is fed a regulated sampling rate signal for this purpose.
Connected downstream of the sampling circuit is a subtractor circuit which subtracts the estimate signal calculated by the echo compensation circuit from the sampled digital received signal by generating an echo-compensated digital received signal. The echo compensation circuit uses the received transmitted data symbols to calculate the echo signal to be expected, and subtracts the latter from the received signal. The echo compensation circuit is adaptively adjustable as a rule. The echo compensation circuit is set adaptively as a function of the transfer function of the transmission line and the analog components, such as the transformer, for example.
The differential signal formed by the subtractor is fed to an amplitude regulation circuit AGC (Automatic Gain Control). The amplitude-regulated digital received signal is subsequently equalized by an equalizer. The downstream decision device uses the equalized received signal to determine an estimate for the transmitted data symbol originally emitted by the other transceiver. The transmitted data symbol obtained is supplied to the data sink for further data processing by the transceiver. A subtractor subtracts the signal values upstream and downstream of the decision device. This error signal or deviation signal serves as adjusting signal for the echo compensation circuit.
A control circuit is used to generate a clock regulation criterion or a clock regulation control signal for the regulation of the sampling phase of the received signal. The clock regulation control signal specifies a phase deviation between the signal phase of the sampling rate signal and a desired setpoint signal phase of an ideal sampling rate signal. The clock regulation criterion or the clock regulation control signal is a measure of the phase error between the ideal sampling rate, for which a maximum signal-to-noise ratio exists, and the actual sampling rate. The clock regulation control signal is generated by the control circuit from the samples upstream and downstream of the decision device (decision feedback regulation) and, furthermore, from at least one of the coefficients of the linear equalizer EQ. The clock regulation criterion or the clock regulation control signal is composed in this case of two components, specifically of a signal component which is a function of the samples upstream and downstream of the decision device, and of a second signal component, which is a function both of one or more coefficients of the linear equalizer and of a phase reference signal value which is suitably prescribed and applied to the control circuit. Given an optimally adjusted sampling phase, the signal component which is a function of the coefficient corresponds to the prescribed phase reference signal value. The control circuit therefore continuously generates a control variable which is a measure of the deviation of the sampling phase from the setpoint phase.
The generated clock regulation control signal is supplied to a digital loop filter. The output signal of the loop filter directly regulates the sampling phase of the sampling rate signal for the sampling circuit. This is implemented as a rule with the aid of a phase counter.
The time-continuous received signal is sampled in the digital receiver of the transceiver with the aid of a receiver symbol clock. Since the symbol clock of the original transmitted signal is unknown at the receiving end, the symbol clock of the received signal is generated by means of the clock phase regulation circuit. The clock signal is derived from the received signal for this purpose. This is also denoted as self synchronization. In addition to the symbol clock frequency, the correct sampling phase is also adjusted by means of the clock regulation loop.
FIG. 3 shows an adaptive equalizer according to the prior art. The output signal of the amplitude regulation circuit AGC is fed to a chain of delay elements whose output signal are [sic] multiplied in each case by a filter coefficient Ci of the equalizer. The output signals weighted with the filter coefficients are fed to an adder and summed up there. The output signal of the adaptive equalizer y(k) is fed to the decision device within the transceiver in accordance with FIG. 2.
FIG. 4 shows a control circuit within a transceiver according to the prior art. The control circuit serves to generate a clock regulation control signal which specifies the phase deviation between the signal phase of the sampling signal and a setpoint signal phase of an ideal sampling signal. This clock regulation control signal is filtered by the downstream loop filter and fed to the phase counter in order to generate the sampling rate signal. The control circuit includes a calculation circuit for calculating a clock regulation criterion u(k) as a function-of the equalized digital received signal y(k) and the digital estimate signal a(k) at the output of the decision device. As digital output signal of the calculation circuit, the clock regulation criterion u(k) formed is multiplied by a first scaling factor SK1 and fed to an adder. The filter coefficients Ci of the adaptive equalizer are tapped and multiplied by stored decoupling coefficients gi. An adder adds the output signals of the multiplier to a stored phase signal reference value. The output signal of the adder is zero in the steady state. The output signal of the adder is multiplied by a second scaling factor SK2 and subsequently summed up by the summation circuit with the scaled clock regulation criterion to form the clock regulation control signal. The decoupling coefficients gi, which are preferably stored in a memory, are adjusted as a function of the data transmission channel, and are multiplied by the filter coefficients ci of the adaptive equalizer in order to decouple the adaptive equalization from the clock regulation.
FIG. 5a shows a calculation circuit for the clock regulation criterion within the control circuit according to the prior art.
FIG. 5b shows a further known calculation circuit for a clock regulation criterion within the control circuit according to the prior art.
The calculation circuits according to the prior art which are illustrated in FIGS. 5a, 5b are so-called Mueller and Müller synchronizers such as are described, for example, in “Timing recovery in digital synchronous data receivers” IEEE Trans. Commun. volume COM 24, pages 516-531, May 1976. The Müller-Müller sampling phase error detectors as illustrated in FIGS. 5a, 5b exhibit a relatively large phase jitter for transmission links H whose pulse responses extend over a relatively large number of clock cycles T. Phase jitter leads to a worsening of the bit error rate.
The clock phase regulation circuit according to the prior art which is illustrated in FIGS. 2 to 5 has the disadvantage that in the case of a data transmission system with excess bandwidth such as, for example, HDSL-2, HDSL-4 or else SDSL it does not permit stable clock regulation, since the mean value of the clock regulation criterion does not exhibit a monotonically rising zero crossing around the sampling instant.
The excess bandwidth is greater than the minimum bandwidth. The minimum bandwidth for data transmission is half the symbol rate, that is to say the minimum bandwidth=½×symbol clock rate=½×1/T.
FIG. 6a shows a distortionless received pulse of a transceiver in the case of a data transmission system without excess bandwidth and with a rolloff factor of 0.2.
FIG. 6b shows the mean value of the clock regulation criterion u(k) according to the prior art formed by the calculation circuit within the control circuit. The conventional calculation circuits illustrated in FIGS. 6a [sic], 5b for calculating the clock regulation criterion u [lacuna] led to a propagation time delay of T. The received pulse illustrated in FIG. 6a is completely distortionless, that is to say no symbol interference occurs. The zero crossings of the received pulse are situated exactly at multiples of the symbol clock pulse T. The maximum of the distortionless received pulse illustrated is at the symbol clock pulse 4×T in FIG. 6a. The sampling instant, which is one symbol clock pulse later (1×T) in the case of the calculation circuits illustrated in FIGS. 5a, 5b, is in a monotonically rising region of the calculated mean value u. The characteristic line has a monotonically rising profile about the sampling instant 5×T, and so a stable clock phase regulation is ensured when there is no excess bandwidth. The characteristic line runs in an approximately linear fashion about the sampling instant 5×T.
In a conventional transceiver as illustrated in FIG. 2, the excess bandwidth is determined by the transmitting filter SF and the receive filter EF. FIG. 7a shows a distorted received pulse of a transceiver with a rolloff factor=0.2 and an excess bandwidth of 50%. In the case of the received pulse, distortions of the received signal occur owing to the excess bandwidth. The zero crossings of the received pulse no longer lie in the clock pulse symbol array or at the multiple of the symbol clock pulse T. FIG. 7b shows the profile of the mean value of the clock regulation criterion calculated by the conventional calculation circuit. In the region of the sampling instant (5×T), the mean value formed exhibits not a monotonically rising or falling profile, but an S-shaped profile with a point of inflection. No monotonically rising or falling zero crossing is present in the region of the sampling instant. In the case of the conventional clock phase regulation circuit according to the prior art the regulating characteristic is not approximately linear, and therefore also not stable, in the region of the sampling instant for a data transmission system with excess bandwidth.
Again, in the case of the conventional clock phase regulation circuit the equalizer provided in the transceiver cannot prevent the occurrence of unstable regulation, as may be seen from FIG. 8. FIG. 8 shows the case of a received pulse, originally received in a distorted fashion, which is equalized by the equalizer provided in the transceiver, the data transmission system having an excess bandwidth of 50%. As may be seen from FIG. 8b, in the region of the sampling instant the profile of the mean value for the clock regulation criterion calculated by the conventional calculation circuit is likewise S-shaped. Even given equalization by an equalizer, there is no monotonically running zero crossing in the region of the sampling instant, and so stable clock phase regulation is not possible.